Wafer-level packaging fo RF applications : using high resistivity polycrystalline silicon substrate technology

Abstract

High-resistivity polycrystalline silicon (HRPS) wafers are explored as a novel low-cost and low-loss substrate in Wafer-Level Chip-Size Packaging (WLCSP) for RF applications. The WLCSP solution we demonstrate is based on adhesive bonding of a HRPS wafer to a silicon wafer with active devices. After bonding, the IC wafer is thinned below 50 µm and selectively removed to expose its front-side contact pads. The HRPS wafer serves as a mechanical carrier, thermal spreader and vertical spacer in which vias are etched by DRIE to reach desired pads on the IC wafer. Then after a seed layer sputtering, a 5-10 µm Cu layer is plated on both wafer sides and patterned providing a back-side ground plane and large, front-side RF passives. Due to HRPS electrical properties, no dielectric isolation layer is required inside vias, simplifying the front-side processing. Solder bumping on the substrate backside and singulation by dicing complete the processing. The presented concept enables integration of large RF passives with a spacing of >150 µm to the conductive silicon substrate containing the circuitry, while providing mechanical stability, reducing form factor and avoiding any additional RF loss. Antenna performance comparable to glass substrates and high quality factors for large spiral inductors (Q=11 at 1 GHz; 34 nH) are demonstrated. The HRPS substrates have high dielectric constant, low RF loss, high thermal conductivity, perfect thermal matching, and processing similar to the single-crystalline silicon.