Utilize este identificador para referenciar este registo:
https://hdl.handle.net/1822/81645
Título: | A hardware-assisted translation cache for dynamic binary translation in embedded systems |
Autor(es): | Salgado, Filipe Alexandre Andrade Gomes, Tiago Manuel Ribeiro Tavares, Adriano Cabral, Jorge |
Palavras-chave: | Dynamic Binary Translation Embedded systems Computer architectures Hardware Accelerator Constrained devices System-on-chip |
Data: | 1-Jan-2018 |
Editora: | IEEE |
Revista: | IEEE International Conference on Emerging Technologies and Factory Automation - ETFA |
Resumo(s): | Approaches to Dynamic Binary Translation (DBT) on resource-constrained embedded systems are not straight forward, leading to several improvements and acceleration suggestions that rely on dedicated hardware. Software to hardware offloading is a common acceleration procedure used when software-only approaches do not meet the performance requirements, making such approach suitable to be successfully applied to DBT. This article approaches hardware offloading to address some limitations of an in-house DBT engine, the DBTOR, regarding its Translation Cache (TCache) management mechanism. The suggested approaches are non-intrusive to the target architecture, which cope with the commercial-off-the-shelf (COTS)-driven deployment of DBT for the resource-constrained embedded devices. This work proposes a TCache management hardware module that overpasses the linked list and hash table software-only approaches, resulting in a performance improvement of 25% and 26%, respectively. |
Tipo: | Artigo em ata de conferência |
URI: | https://hdl.handle.net/1822/81645 |
ISBN: | 978-1-5386-7108-5 |
DOI: | 10.1109/ETFA.2018.8502558 |
ISSN: | 1946-0740 |
Arbitragem científica: | yes |
Acesso: | Acesso aberto |
Aparece nas coleções: |
Ficheiros deste registo:
Ficheiro | Descrição | Tamanho | Formato | |
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A_Hardware-assisted_Translation_Cache_for_Dynamic_Binary_Translation_in_Embedded_Systems.pdf | 278,81 kB | Adobe PDF | Ver/Abrir |